PRESTO ENGINEERING AND CADENCE COLLABORATE ON IC PACKAGING FOR AUTOMOTIVE AND IOT MARKETS

Presto Engineering, an ASIC design and outsourced operations provider, and Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced a collaboration to broaden semiconductor package design solutions and expertise for high-performance system-in-package (SiP) development for the automotive and Industrial IoT markets. Presto is adopting the Cadence^® system design and analysis portfolio for advanced IC packaging, which includes the Cadence Allegro^® X Package Designer Plus, Clarity 3D Solver, Sigrity XtractIM technology and Celsius Thermal Solver, on an exclusive basis in order to design IC packaging solutions for its automotive and IoT customers. In addition, Presto plans to provide Cadence with input on software features, functions and workflows specific to Cadence’s end customer and market needs.

“We are pleased to collaborate with Cadence, a leader in electronic design software, system-level analysis, hardware and IP,” said Cédric Mayor, vice president global strategy and corporate development at Presto. “Our ability to leverage the Cadence packaging design and analysis workflow will help us broaden our design services for IC packaging customers needing tailored capabilities and specific requirements. In our efforts to date, we have already seen a 50 percent faster turnaround time due to a reduction in design iterations enabled by Cadence technologies.”

“Developing today’s complex semiconductor packages, such as heterogeneous SiPs with 3D chip stacks and high-speed data transfer packages, requires a high level of collaboration between IC designers and package engineers,” said KT Moore, vice president, product management in the Custom IC & PCB Group at Cadence. “With no two package designs being alike, collaborating with Presto allows us to capture insights on state-of-the-art package design trends as well as design team collaboration and workflow productivity.”

SiP and 3D packages, especially those with high-reliability requirements, tend to require multiple spins in order to optimize the bill of materials and design tolerances, as well as to achieve full control of the chip’s performance reproducibility. Cadence solutions, coupled with manufacturing knowledge and planning during the design process, help to reduce design spins and speed time to market.

Presto’s ability to provide a full suite of analytical qualification services within a single facility further reduces the time to market for its customers. The Cadence system design and analysis portfolio for advanced IC packaging supports Cadence’s Intelligent System Design strategy, enabling SoC design excellence. Now, with the addition of the Cadence portfolio, Presto offers a full set of design and qualification tools to help customers achieve the most efficient design-for-manufacturing (DFM) process, strengthening its position as the Trusted Microelectronics Partner.

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