STM32MP21 targets cost-efficient, secure edge computing
STMicroelectronics expands the STM32MP2 series with the STM32MP21 MPUs, combining low power consumption, flexible performance, and a security architecture aligned with industrial and IoT requirements.
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STMicroelectronics has introduced the STM32MP21 microprocessor family to address cost-sensitive edge applications in smart factories, smart homes, and smart cities. The new devices extend the STM32MP2 series with a focused feature set aimed at balancing processing performance, power efficiency, long-term availability, and regulatory-grade security.
Heterogeneous architecture for edge workloads
The STM32MP21 integrates a 64-bit Arm Cortex-A35 core running at up to 1.5 GHz alongside a 32-bit Cortex-M33 core operating at up to 300 MHz. This heterogeneous architecture enables separation of application-level processing and real-time control. The Cortex-M33 can also manage early boot tasks, enabling faster system startup and reduced wake-up latency from low-power modes.
This approach allows designers to allocate workloads flexibly while optimizing overall energy consumption, which is critical for always-on or intermittently active IoT and industrial systems.
Connectivity, vision, and deterministic networking
The MPUs integrate MIPI CSI-2 interfaces and an image signal processing (ISP) pipeline, supporting machine-vision use cases such as industrial inspection and barcode or QR-code reading. Dual Gigabit Ethernet ports with Time-Sensitive Networking (TSN) are included to support deterministic, low-latency communication required in industrial automation, robotics, and sensor data acquisition.
Memory flexibility is a key design element. In addition to DDR4 and LPDDR4, the STM32MP21 supports DDR3L, enabling designers to mitigate supply constraints, optimize bill of materials, and maintain competitive system pricing.
Security architecture aligned with regulation
The STM32MP21 shares the STM32MP2 series security architecture, targeting SESIP Level 3 and PCI pre-certification. This aligns with upcoming regulatory frameworks such as the EU Cyber Resilience Act. Protection mechanisms include secure boot, hardware cryptographic acceleration, Arm TrustZone-based isolation, and ST’s proprietary Resource Isolation Framework to protect memory and peripherals.
Devices are provisioned during manufacturing using ST’s secure secret provisioning process, embedding unique identities and immutable credentials before delivery.
Power management and development ecosystem
ST has introduced the STPMIC2L power-management IC as a companion device for the STM32MP21, supplying the MPU and associated DRAM while reducing board complexity and footprint. Additional PMIC options support other STM32MP2 configurations.
Developers can leverage the STM32 ecosystem, including OpenSTLinux distributions (Yocto and Buildroot), ST Edge AI tools, evaluation boards such as the STM32MP215F-DK, and reference designs. A bare-metal software option for the STM32MP2 series is planned for 2026.
Adoption and availability
Early customer engagement includes companies such as JVCKENWOOD, which has evaluated the STM32MP21 for low-power, cost-conscious designs requiring flexible peripherals and long-term supply stability.
The STM32MP21 is offered in multiple package options suitable for both 4-layer and 6-layer boards, with pin-to-pin compatibility across the STM32MP2 series for certain variants. Pricing ranges from approximately USD 5.70 to USD 8.50 in 1,000-unit quantities. As industrial-grade products, the devices are covered by ST’s 10-year longevity program.
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