CEVA ANNOUNCES ITS MOST POWERFUL AND EFFICIENT DSP ARCHITECTURE TO DATE

CEVA, Inc., the leading licensor of wireless connectivity and smart sensing technologies and co-creation solutions, recently announced its 5th generation CEVA-XC DSP architecture and its most efficient to date, the CEVA-XC20.

The new CEVA-XC20 is based on a groundbreaking vector multi-threaded massive compute technology that is designed to address next-generation 5G-Advanced workloads across a broad spectrum of use cases, including smartphones, high-end Enhanced Mobile Broadband (eMBB) devices and a range of cellular infrastructure devices.

The CEVA-XC20 architecture was designed in consultation with CEVA's leading Tier 1 OEM customers, with the common aim of improving mobile network performance and power efficiency. The CEVA-XC20 solves the performance challenges posed by next-generation compute-intense 5G-Advanced by employing a novel Dynamic Vector Threading (DVT) scheme, which supports true hardware multi-threading, which up until now was only found in general-purpose CPU architectures.

The first core based on the CEVA-XC20 architecture is the CEVA-XC22 DSP, supporting two execution threads using the groundbreaking DVT scheme. The CEVA-XC22 offers a 2.5X improvement in efficiency (performance per watt and area) for essential 5G use cases and computation kernels versus its predecessor.

The CEVA-XC22 DSP will be available for general licensing in the second quarter of this year. CEVA-XC22 customers can also benefit from ASIC/SoC co-creation services by CEVA's Intrinsix team to help integrate and support system design and modem development.