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IAR Systems and Codasip collaborate to enable low-power RISC-V-based applications

The professional development tools IAR Embedded Workbench for RISC-V now support Codasip’s low-power embedded processors.

IAR Systems and Codasip collaborate to enable low-power RISC-V-based applications

IAR Systems®, the world leader in software tools and services for embedded development, and Codasip®, the leading supplier of customizable RISC-V processor IP, today announced their partnership enabling joint customers to build low-power embedded applications based on RISC-V. Following this, version 2.11 of IAR Embedded Workbench® for RISC-V now supports the L30 and L50 processors from Codasip. The L30 and L50 are small and energy-efficient low-power embedded processor cores from Codasip, all fully customizable and adaptable to the unique needs of a project.

IAR Embedded Workbench for RISC-V is a complete C/C++ compiler and debugger toolchain with everything embedded developers need integrated in one single IDE. Through its excellent optimization technology, IAR Embedded Workbench for RISC-V helps developers ensure the application fits the required needs and optimize the utilization of on-board memory.

“Codasip L30 and L50 RISC-V processors are fully compliant with RISC-V specification allowing customers to choose from a variety of compilation and debug solutions,” said Zdeněk Přikryl, Chief Technology Officer, Codasip. “IAR Systems is a market leader in the embedded space and our processors work flawlessly with IAR Embedded Workbench”.

“The Codasip L30 and L50 are powerful additions to the embedded RISC-V ecosystem,” said Anders Holmberg, Chief Technology Officer, IAR Systems. “We are committed to supporting both new and existing technology partners, as well as customers in making the most out of their investments in RISC-V by continuously expanding our RISC-V product portfolio."

Both Codasip and IAR Systems are participating in the RISC-V Summit 2021 which is collocated with the 58th Design Automation Conference (DAC) in San Francisco, California, on December 6-8, 2021. For details of Codasip’s #RISCVSummit keynote or to arrange a meeting at either event, visit Codasip here.

More information about IAR Systems’ offering for RISC-V is available at www.iar.com/riscv. More information about Codasip’s RISC-V processor cores is available at www.codasip.com.

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